1. Field
Advancements in microprocessor system DRAM accessing and microprocessor system DMA processing are needed to provide improvements in performance, power efficiency, and utility of use.
2. Related Art
Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes. Nothing herein is to be construed as an admission that any of the references are pertinent prior art, nor does it constitute any admission as to the contents or date of actual publication of these documents.
In some microprocessor systems DRAM accesses are performed during DMA operations (such as GPU references to frame buffer information) when other processing in the system is minimal or suspended, and each of the DRAM accesses consumes significant power. Similarly, in some microprocessor systems all or portions of an otherwise powered-down processor and associated cache sub-system are powered up (or are prevented from powering down) to process coherent DMA operations (such as a USB device transaction). What are needed are more effective techniques of performing DRAM accesses and processing DMA accesses, thereby enabling improvements in performance, power efficiency, and utility of use.
In ACPI-compliant systems, coherent DMA is disallowed for low-power ACPI-compliant states C3, C4, C5, and so forth, as there is no snooping, while coherent DMA is allowed for relatively higher-power ACPI-compliant states C2, C1, and C0, as caches are snooped. Hereinafter the terms C0, C1, C2, C3, C4, and C5 are meant to refer to like-named ACPI-compliant power states.